This invention relates to methods of manufacturing a trench-gate semiconductor device, for example an insulated-gate field-effect power transistor (commonly termed a "MOSFET") or an insulated-gate bipolar transistor (commonly termed an "IGBT"). The invention also relates to semiconductor devices manufactured by such a method.
Such trench-gate semiconductor devices are known having source and drain regions of a first conductivity type separated by a channel-accommodating body region of the opposite second conductivity type. An advantageous method of manufacture is disclosed in United States patent U.S. Pat. No. 5,378,655 (our reference PHB 33836), in which the formation of the source region is self-aligned with the trench (also termed "groove") which comprises the gate. The self-alignment is achieved by forming a second mask from a first mask, by the provision of sidewall extensions on the first mask. These sidewall extensions act as self-aligned spacers. The method of U.S. Pat. No. 5,378,655 includes the steps of:
(a) forming an etchant mask on the device body having a window at an area of a region of the second conductivity type in the body where the gate and channel are to be formed, PA1 (b) etching the trench into the device body at the window to extend through the region of the second conductivity type and into an underlying portion of the drain region, PA1 (c) providing a gate in the trench where the region of the second conductivity type provides the channel-accommodating region, and then providing a mask (the "first" mask) over the gate in the trench, this first mask forming a protruding step to the adjacent surface of the body, (optionally forming a layer of the first conductivity type at the window in the first mask), PA1 (d) forming the second mask with a smaller window by providing sidewall extensions of the first mask at the step, PA1 (e) forming the source region by etching away the first-conductivity-type layer at the area of the window in this second mask or by introducing dopant of the first conductivity type from these sidewall extensions into the region of the second conductivity type, and then PA1 (f) providing a source electrode at the surface of the body, so as to contact the source region and the adjacent surface region of the second conductivity type.
U.S. Pat. No. 5,665,619 describes a modified extension of this known method, in which the trench is defined and filled with silicon gate material using an etchant mask which is of complementary window pattern to the first mask and comprises silicon nitride. The silicon nitride masks underlying areas of the body against oxidation while oxidising an upper part of the gate material to form the first mask. Being of a differently-etchable material (silicon nitride) from the first mask (silicon dioxide), a subsequent etch-removal of the silicon nitride leaves the first mask (silicon dioxide) as the desired protruding step. However, some lateral oxidation of the silicon body surface does occur at the edge of the silicon nitride so resulting in a so-called "bird-beak" shape to the stepped edge of the first mask. It is difficult to control the lateral extent and step shape of this bird-beak. The whole contents of both U.S. Pat. No. 5,378,655 and U.S. Pat. No. 5,665,619 are hereby incorporated herein as reference material. By using such techniques as disclosed in U.S. Pat. No. 5,378,655 and U.S. Pat. No. 5,665,619, the number of photolithographic masking steps which require separate alignment can be reduced and compact cellular device structures can be formed.
Trench-gate semiconductor devices are also known in which the channel-accommodating body region is of the same, first conductivity type as the source and drain regions. In this case, the conductive channel is formed by charge-carrier accumulation by means of the trench-gate. Similar considerations arise with respect to the doping of the regions and the etching of the trench, as in the more usual device in which the channel-accommodating region is of the opposite, second conductivity type.